Phase change memory devices are employed in many areas of information storage. Presently, phase change memory devices, especially nonvolatile memory cells, are being scaled down to the 45 nanometer node and lower. For scaled down devices, the amount of current required to melt and modulate the chalcogenide phase change material must be reduced. Chalcogenide material useful in phase change memory devices can be germanium-antimony-tellurium (GST). Instead of employing GST, other chalcogenide materials can be used as the phase change material in the memory devices.
Reduction of current can be accomplished in two ways. A first method of reducing current is by decreasing the size of the contact electrode or diode. The contact electrode or diode is the contact that meets the chalcogenide material. In the alternative, the contact, which can be an electrode or a diode, can be located adjacent to a heating element. The heating element then directly contacts the phase change material. The contact electrode or diode extends from a base electrode. In a second method, the volume of the phase change material itself can be reduced.
The first method of reducing current requires consistency in lithographic methods employed in forming the downsized electrodes. The first method of reducing current also requires efficient methods of depositing contact material over the base electrode.
WO 2007093190 discloses a nonvolatile memory cell comprising a phase change material for storing information. The phase change material is electrically contacted with ends of carbon nanotubes at specific contact regions. The carbon nanotubes have an upper surface coating made of an electrically conductive material. Contact regions that have a small surface area are obtained. Said contact regions are prepared in an efficient and reproducible manner.
US Patent Application Publication No. 2007/0158697 discloses a method for fabricating a phase change memory device comprising disposing a catalyst for forming a plurality of carbon nanotubes over predetermined regions of the current source electrode supplying external current necessary for inducing a phase change; vertically growing carbon nanotubes using the catalyst as a seed to thereby form the carbon nanotube electrodes; depositing an insulation layer over the current source electrode in a manner to cover the carbon nanotube electrodes; polishing the insulation layer until the insulation layer is flushed with the carbon nanotube electrodes; depositing a heat generating resistance layer in contact with the carbon nanotube electrodes exposed substantially at the same level of the planarized insulation layer; and forming a phase change material layer over the heat generating resistance layer. See paragraph [0105] of the application.
US Patent Application Publication No. 2007/0012956 discloses a method for fabricating a memory cell device. The method comprises providing a preprocessed wafer having a landing pad; depositing a first insulation material layer over the preprocessed wafer; depositing a second insulation material layer over the first insulation material layer; applying a photoresist layer over the second insulation material layer; etching an opening through the second insulation material layer and the first insulation material layer to expose the landing pad; depositing a catalyst material layer over the photoresist layer and the landing pad; removing the photoresist layer and the catalyst material layer on the photoresist layer leaving the catalyst material layer on the landing pad; growing a first electrode selected from the group consisting of a nanotube, a nanowire, and a nanofiber on the catalyst material layer; depositing a third insulation material layer over exposed portions of the second insulation material layer, the first insulation material layer, the landing pad, and the first electrode; planarizing the third insulation material layer to expose the second insulation material layer; depositing phase-change material over the second insulation material layer, the third insulation material layer, and the first electrode; depositing electrode material over the phase-change material; and etching the phase-change material and the electrode material to form a second electrode and a storage location. See claim 28 of the publication.
US Patent Application Publication No. 2006/0131555 discloses a method of forming a memory element. The method comprises forming a first electrode comprising at least one conductive nanostructure; forming a second electrode; and forming a resistance variable material layer between the first and second electrodes, the first electrode formed electrically coupled to the resistance variable material. The first electrode can be a nanowire. See claim 33 of the publication.
US Patent Application Publication No. 2004/0251551 discloses a method for forming an integrated circuit phase changeable memory device. The method comprises forming a lower conductive pattern on an integrated circuit substrate; forming an insulating layer on the substrate, the insulating layer having a contact hole exposing the lower conductive pattern; growing a carbon nanotube on the lower conductive pattern exposed by the contact hole; forming a supporting insulating layer on the insulating layer and the carbon nanotube; planarizing the supporting insulating layer to expose the carbon nanotube; and forming a phase changeable material pattern and an upper conductive pattern on the carbon nanotube that is exposed. See claim 27 of the publication.
US Patent Application Publication No. 2004/0211953 discloses an electronic PCM device. The device comprises a body of semiconductor material having lower surface; a dielectric layer extending on top of the body; and a PCM memory cell that includes a PCM storage element formed in the dielectric layer and a selection element, the storage element being formed by a heater element and a storage region, the storage region being of chalcogenic material and being in electric contact with the heater element, wherein the heater element has an end face extending transversely to the lower surface and forming a contact area with the storage region. See claim 16 of the publication.
U.S. Pat. No. 7,122,824 discloses an electronic PCM device. The device comprises a body of semiconductor material having a lower surface; a dielectric layer extending on top of the body; and a PCM memory cell that includes a PCM storage element formed in the dielectric layer and a selection element, the storage element being formed by a heater element and a storage region, the storage region being of chalcogenic material and being in electric contact with the heater element, wherein the heater element has an end face extending transversely to the lower surface and forming a contact area with the storage region, wherein the selection element is formed in the body, a lower electrode extends in the dielectric layer between the selection element and the heater element and an upper electrode extends in the dielectric layer on the storage region and forms a bit line. See claim 11 of the '824 patent.
None of the above references, taken either together or separately, serve to anticipate the present invention as disclosed and claimed below.